Cu Barrier and Adhesion Layer Deposition
A number of techniques for depositing engineered adhesion and diffusion barrier layers for copper metallization technology have been developed at Tegal for which patents have been awarded. These patents include graded adhesion layers, nitrided diffusion barriers, and methods for damage-free deposition on sensitive low-k dielectrics.
Copper Seed Layer
Two important aspects of Copper interconnect technology have played a crucial role in device fabrication in recent years: Cu fill and dielectric constant. Cu fill has historically been accomplished with PVD, and more recently ionized PVD, to satisfy the process requirements for advanced chips. The evolution in fill technology has been driven largely by the aspect ratio in the damascene interlayer dielectric structure. As the sizes of these features have decreased, feature filling has required increasingly complex process and hardware technology.
To continue the evolution of new device generations, particularly in FLASH memory devices, aspect ratio requirements will drive the need to replace iPVD with alternative technologies such as ALD and NLD to satisfy advanced copper fill requirements.The adoption of ALD and NLD processes into device fabrication lines requires new integrated process flows to overcome differences in PVD and ALD process requirements. ALD, for example, requires an adhesion layer between the barrier layer and the copper seed layer that has not historically been needed for PVD integration schemes. A number of materials are currently being investigated to replace the currently utilized Cu seed layer, for example, in copper fill process flows that utilize ALD for the seed layer deposition.
The patents in Tegal's portfolio provide a number of options for depositing films and structures that address the adhesion issue in ALD-based process flows for pre-Cu-fill barrier, adhesion, and seed layer deposition.
Low-k Dielectric
Efforts continue to be made to reduce the dielectric constant of the interlayer material in copper interconnect technology in order to drive down RC delay times. The past successes of introducing carbon and fluorine to SiO2 matricies to drive down the dielectric constant have been replaced with efforts to introduce porous materials. The ITRS Roadmap calls for several generations of low-k dielectrics in a range for which porous materials are showing, or have already shown, to be the best candidates.
A critical step in the integration of low-k dielectrics, covered in the Tegal portfolio in an integrated process, is the removal of moisture and other contaminants prior to the deposition of a capping layer to prevent drift in the dielectric properties of the low-k material. Another patent describes a process for minimizing potential damage in polymeric low-k dielectric films that represent an alternative to porous low-k dielectrics.
Summary
Atomic layer deposition of conductive copper barrier layers, adhesion layers, and seed layers, combined with porous low-k dielectrics have been identified as the most probable candidates for the extension of CMOS technology to future device generations in the ITRS roadmap. The Tegal portfolio contains a group of patents specifically grouped for their relevance to the ITRS roadmap.
